module top_module(
    input clk,
    input areset,
    input train_valid,
    input train_taken,
    output [1:0] state
);

	localparam SNT=2'b00;
	localparam WNT=2'b01;
	localparam WT=2'b10;
	localparam ST=2'b11;
	
	reg [1:0]state_r;
	reg [1:0]next_state_r;
	
	always@(posedge clk or posedge areset)begin
		if(areset)begin
			state_r<=WNT;
		end
		else begin
			state_r<=next_state_r;
		end
	end
	always@(*)begin
		if(train_valid)begin
			case(state_r)
				SNT:next_state_r=(train_taken)?WNT:SNT;
				WNT:next_state_r=(train_taken)?WT:SNT;
				WT:next_state_r=(train_taken)?ST:WNT;
				ST:next_state_r=(train_taken)?ST:WT;
			endcase
		end
		else begin
			next_state_r=state_r;
		end
	end
	
	assign state=state_r;
	
endmodule